One-third the area and same performance vs. standard SOIC packages
Same outline with 72% RDS(on) reduction vs. industry-best TSOP-6
Ultra low RDS(on) based on IR HEXFET® trench MOSFET technology
Equivalent or better thermal performance
Low profile at <0.8mm
Virtual elimination of package parasitics devices
Compatibility with standard SMT techniques
Fully electrically tested, delivered in tape-and-reel
.pdf Version
FlipFET™ Packages Enabling World’s Highest Power Density
APPLICATIONS
High-end cell phones
Notebook computers
Digital cameras
MP3 Players
SPECIFICATIONS
Part Number
BVDSS
VGS
RDS(on)
TJ(max.)
Configuration
IRF6100
-20V
12V
65mW
150°C
Single P
IRF6150
-20V
12V
36mW
150°C
Dual P,
Common Drain
New FlipFET™ packages embody true chip scale packaging (CSP) technology, giving rise to a new generation of super-compact power architectures with increased power density. Achieving the world’s first 100% silicon-to-footprint ratio, any of IR’s low-voltage HEXFET power MOSFETs in this new package provide the smallest footprint, lowest profile, and lightest weight solution possible for a MOSFET. In this new proprietary package, all of the terminals are on a single side of the die. The die is the package, so stray inductance and other losses associated with device packaging are minimized or eliminated. With this new FlipFET package, footprints are reduced by more than 70 percent to one-third those of popular TSOP-6 and SO-8 packages while providing the same or better performance.
HEXFET® Power MOSFETS with a 100% Silicon-to-Footprint Ratio
Application Notes
AN-1011: Assembly of FlipFET™ Devices
Technical Papers
Bi-directional FlipFET™ MOSFETs for Cell Phone Battery Protection Circuits
FlipFET™ MOSFET Design for High Volume SMT Assembly
Chip Scale Packaging Technology Increases Cell Phone Talk Time
A New Generation of Wafer Level Packaged HEXFET® Devices
For more information:
Contact the Technical Assistance Center or your local Sales Rep. Home