Accelerator™ Motor Control Design Platform

The Accelerator Motor Control Design Platform is an FPGA-based re-configurable signal processing architecture using soft peripherals that achieves unmatched motor control performance with feedback control loop bandwidth up to 5kHz (fig 1.)

The Accelerator Design Platform is demonstrated with the LACB101 full-featured servo control Development System that uses an advanced all-in-one tool for simulation and synthesis of digital servo drive algorithms based on an industrial quality hardware platform. The LACB101 Development System consists of the LACS101 hardware platform, which allows limited algorithm configurability and evaluation, even in stand-alone mode, and the LACV101 code generation tool, which provides the complete software toolset needed for servo algorithm development and code generation.

Fig 1. Torque Control Bandwidth Comparison
The Accelerator Advantage

Highest closed-loop motor control bandwidth available in the market today
High speed parallel execution FPGA supports advanced Field Oriented Control and PWM Algorithms
Analog bandwidth with the flexibility of digital control
Servo Toolbox cuts “Idea-to-Prototype” development time by half
Graphical design approach using drag and drop control block primitives and functional modules in Simulink™
Fully developed and tested servo-specific Verilog™ modules
State-of-the-art hardware platform utilizes L’s proven power management IC’s and switches

Aerospace flight controls and automotive drivetrain controls
Automated assembly, precision material handling and machining equipment
Control Algorithm Research for single and multi-axis permanent magnet AC and induction motor drives
Educational / Instructional / research use
Test/evaluation of motors and motor controls
Part Number Title
LACB101 Complete bundled servo control development system (contains LACS101 and LACV101)
LACS101 Pre-configured Hardware Evaluation Platform with GUI
LACV101 Code Generation Tools with Matlab to Verilog Porter, Control Libraries, and complete FOC algorithm
LACS101Hardware Platform
Pre-configured Hardware Evaluation Platform with GUI shown with 400W PMAC ServoFeatures at a Glance:

Stand-alone evaluation of pre-configured control code
High Speed Hardware Processor (FPGA) Executes complete FOC loop in less than 2uSec
High Speed Isolated 6.5Mbaud Serial Host Computer interface
Utilizes IR’s latest HVIC Gate Drive and Current Sense IC’s that offer faster speed and lower delays than opto-couplers
Includes 1.5KW, 600V IGBT Power Stage with Brake and Input Rectifier

Fig 2. IRACS101 Block Diagram
LACV101 Accelerator Servo Toolbox
Code Generation Tools with Matlab to Verilog Porter, Control Libraries, and complete FOC algorithm.

Fig 3. Accelerator Servo Toolbox
Features at a Glance:

Integrates all necessary system, gate Level and physical layout tools on a common platform
Matlab to Verilog Porter (MVP) tool translates system-defined algorithms to gate level source code.
Libraries include modules for Motion Peripheral (such as Sine & SVM PWM), Communication, Sensor Interface and Control Primitives specific to servo control.
Complete FOC algorithm source code for high performance servo

Achieving The Highest Control Loop Bandwidth

Many of today’s demanding servo motor applications such as high speed factory automation systems, and fly-by-wire/drive-by-wire vehicle control require higher levels of timing performance than ever before. Figure 4 shows how high performance servo control functions are divided into two basic parts. The hardware rich environment requires fast computation for inner loop torque control, but with relatively less memory. The software intensive environment requires a large memory area for data handling and outer loop control and timing is less critical. A single DSP or MCU using a real-time multi-tasking operating system has difficulty performing these diverse tasks in a timely manner due to all the resource multiplexing and context switching that is needed. While a high performance programmable DSP can execute an FOC loop in a 15-20microsecond period, the Accelerator FPGA-based Hardware Processor does it in 1.5-2microseconds.

Fig 4. Timing Performance Requirements for High Speed Servo Systems.. Enlarge

The Accelerator Motor Control Design Platform leverages the advantage of configurable processors in a revolutionary new approach using a parallel hardware controller/signal processor, which achieves the bandwidth of analog control while providing the flexibility and improved performance features of digital control.

The power of the Accelerator Design Platform rests upon the convergence of three critical technologies:

  1. Dedicated parallel hardware control afforded by the powerful, high speed FPGA-based Configurable Hardware Processor, which allows fast, deterministic algorithm execution and customized power management and motion peripherals.
  2. The Accelerator Servo Toolbox, containing powerful system to gate level porting tools (MVP), key to simplifying the whole design process, and enabling graphical based as opposed to text language design entry.
  3. The use of Lambdaaa’s advanced high voltage power management ICs and Switches, optimized for motor control and recognized throughout the industry for cost effective, efficient gate drive, sensor signal processing, and power switching.

At the heart of Accelerator Design Platform, the Configurable Hardware Processor contains the entire Field Oriented Control (FOC) and customized power management peripherals aimed at the time critical functions required for high performance permanent magnet, and induction machine control (Fig 5).

Fig 5. FOC Algorithm Contained in The Configurable Hardware Processor. Enlarge

The Accelerator Configurable Hardware Processor avoids the bottlenecks faced by traditional microcontroller/DSP architectures with instruction based execution and multiplexed ALU’s, instead using a large number of math processing resources configured in parallel fashion to attain computational speeds more than twenty times that of traditional DSPs, and resulting in higher torque control bandwidth as shown below (based on 20kHz carrier frequency using double edge sampling Asymmetrical PWM). This improved performance also gives designers the increased power to perform multi-axis/multi-loop and advanced control strategies and allows customization of power management peripherals.

Developing Custom Motor Control Processing With Accelerator Design Platform

With the LACV101 Acclelerator Toolbox, control algorithms are designed using graphically connected control blocks instead of the traditional text editing method. Now, the servo design process revolves around control algorithm design at the system level rather than software engineering & coding techniques or design of custom peripheral ASICs. Figure 6 shows focus on system level design using the Accelerator Design Platform.

Note: Test Vector Generator Planned for Future Release

Fig 6. Design Flow Using the Accelerator Servo Toolbox

The LACV101 Accelerator Servo Toolbox contains the Control Block Library, which is a complete set of control primitives available in Simulink™, which can be expanded as needed by users who need to create unique peripheral blocks. The LACV101 diagram shows how, using Accelerator’s unique Matlab™ to Verilog Porter (MVP) tool, the Verilog code is generated, synthesized and directly downloaded into the Configurable Hardware Processor to configure the Control Engine’s functionality, relieving the designer of much manual translation or re-hosting effort.

The Verilog Library contains servo-specific, parameterized, fully tested motion peripheral circuit modules for the user to choose from. Current sensing interface module, encoder feedback module, and PWM waveform generator are examples of unique motion peripheral modules. The use of synchronous design practices throughout the Verilog library facilitates the portability of the code unlike software developed for programmable DSP’s, especially for control applications requiring precise timing due to their interrupt driven nature and their pipelined architecture.

The Accelerator design flow provides a smooth, and integrated environment using the same development platform for system level algorithm design as for control of the actual inverter hardware. Servo designers thus have the ability to perform “hardware in the loop” system evaluation with a real, industrial quality servo drive, avoiding the need for iterative bread-boarding of hardware & software (Fig. 7). The Accelerator Servo Development System provides a way for a small team to manage the complete design process while meeting the increasing demand for higher performance.

Fig 7. Using Accelerator Development System to perform Hardware in the Loop System Evaluation

To gain access a more detailed list of products, partial datasheets, and pricing – please register at the Accelerator Development System Product Page.

In addition to these products, offers a design service for custom servo design and ASIC conversion. Contact Accelerator Sales.

Technical Papers

New Digital Hardware Control Method for High Performance AC Servo Motor Drive – Accelerator&$153 Servo Drive Development Platform for Military Application

Integrated Design Platform for Digital Motor Drives

Accelerator – A New Design Platform for High Performance Digital AC Servo Motor Drives

For more information:
Register at the Accelerator Development System Product Page or contact Accelerator Sales.